Comparative study of single precision floating point division using different computational algorithms

<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast computation can apply all cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the speed mantissa module this is used design a 32-bit multiplier crucial feature proposed design, yields higher reduced time. The floating-point divider using fast synthesized Verilog hardware description language has unit subtractor unit. Xilinx Spartan 6 SP605 evaluation platform verify FPGA. Synthesis results provide device utilization propagation parameters for comparative study done with previous work. Input provided IEEE 754 formats.</span>